1. Field of the Invention
The present invention relates to a test structure and a test method for estimating defects at an isolation edge utilizing a C-t (Capacitance-time) measurement method to evaluate an isolation structure in a semiconductor device which is increasingly becoming highly-integrated.
2. Description of the Background Art
In a field of a semiconductor device which is increasingly becoming highly-integrated, development of an isolation structure is critical to an improvement in device integration. The isolation structure refers to a structure for isolating elements which constitute a semiconductor integrated circuit on a semiconductor chip from one another. FIG. 11 is a plan view showing a relation of a wafer, semiconductor chips and a probe. A semiconductor chip 2 is disposed on a wafer 1, and a probe 3 comes into contact with the semiconductor chip 2 to apply a voltage thereto in order to evaluate the isolation structure provided on the semiconductor chip 2.
FIG. 12 is an enlarged perspective view showing a portion where the probe 3 is in contact with the semiconductor chip 2 on the wafer 1. The probe 3 is pressed against a main surface of the wafer 1 almost perpendicularly thereto so as to apply a pressure to the main surface of the wafer 1 inwardly.
FIG. 13 is a cross section taken along the line 13--13 of FIG. 12 observed from the direction of the arrows. In FIG. 13, a field oxide film isolation 5 is provided on the main surface of the wafer 1 to isolate the semiconductor elements from one another and a gate insulation film 6 is contiguous with the field oxide film isolation on the main surface of the wafer 1, being thinner than the field oxide film isolation 5. A gate electrode 7 is disposed on the gate insulation film 6, extending onto portions of the field oxide film isolation 5 near the gate insulation film 6. A depletion layer 8 is created between the wafer 1 and the gate electrode 7 by applying a voltage with the probe 3.
One of process steps of a test for estimating defects at the isolation edge is shown in FIG. 13. For example, evaluation of the isolation structure is implemented by measuring a current which appears at the periphery of a LOCOS edge as described in Japanese Journal of Applied Physics Vol. 30, No. 128, December, 1991, pp. 3634-3637, "Generation Current Reduction at Local Oxidation of Silicon Isolation Edge by Low-Temperature Hydrogen Annealing" by Mikihiro Kimura, Kaoru Motonami and Yasuhiro Onodera.
Specifically describing, oxide capacitance Co is first measured, which is capacitance of a capacitor constituted of the oxide film (gate insulation film) 6 and the gate electrode 7 in a state where no depletion layer is created by a high-frequency signal. Second, the depletion layer 8 is created by applying a step voltage with the high-frequency signal superimposed thereon, and then initial capacitance C.sub.i in this state is measured. Finally, after a time t.sub.F, when the capacitance comes into equilibrium, equilibrium capacitance C.sub.F is measured. A relation between the capacitance and the time in this measurement is shown in FIG. 14.
According to Shroeder and Guldberg's approximation, a lifetime .tau..sub.gm is obtained from Eq.(1) as below: ##EQU1## where n.sub.i and N.sub.B represent intrinsic carrier concentration and substrate impurity concentration, respectively.
A generation current J.sub.gen is derived from the lifetime .tau..sub.gm as expressed in Eq.(2): EQU J.sub.gen =qn.sub.i W.sub.eff .vertline..tau..sub.gm (2)
where W.sub.eff and q represent an effective depletion-layer width and the amount of electric charges, respectively.
As can be seen from FIG. 15, the generation current J.sub.gen includes an inplane component and a peripheral component, that is, inplane generation current J.sub.genA and the generation current at the LOCOS edge J.sub.genP. The generation current J.sub.gen is expressed using the inplane generation current J.sub.genA and the generation current at LOCOS edge J.sub.genP as follows: ##EQU2##
In order to conduct a test of evaluating the isolation structure, it is necessary to extract only the generation current at LOCOS edge J.sub.genP, for example. With variation of area and peripheral length of the LOCOS edge, a graph is made as shown in FIG. 15 using several points of measurement, and the generation current J.sub.genP per unit length is obtained from the slope of the graph. If only the generation current at LOCOS edge J.sub.genP per unit length becomes larger, more defects are found at the LOCOS edge.
In the background-art test structure for estimating defects at isolation edge, a stress is applied to a region where a depletion layer is to be created below the gate electrode 7 since the probe 3 comes into direct contact with the gate electrode 7 which is provided on a region to be evaluated, as shown in FIG. 13, and a recombination center is thereby additionally created. Thus, there arises a problem that the measured value has more errors than a value to be obtained in a measurement under the condition of actual use.